Power Safe Test Pattern Determination and Refinement for Transition Fault Coverage

Nowadays, at-speed scan based testing is used for testing the performance of the given circuit. In the case of At-speed scan based test, excessive capture power due to power risky pattern may cause significant current demand, resulting in the IRdrop problem .In proposed method, all power risky patterns are discarded and considering power safe patterns and refining them.WSA switching activity is used to estimate whether the given pattern is power risky or power safe pattern.LOC clocking scheme, which is widely used to detect transition faults in scan-based designs and the capture power problem.. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. Experimental results on ISCAS’89 andITC’99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and the remaining undetected faults can be detected by the low-power test generation process.